Model card

A model card in DMT collects the parameters inside the collection and the correct model (most times represented by a Verilog-AMS code). So the MCard class has attributes and methods to handle this nicely.

MCard class

class DMT.core.mcard.MCard(nodes_list: list[str], default_subckt_name: str, default_module_name: str, version: str | float = '-', va_file: str | PathLike | None = None, va_codes=None, vae_module=None, directory_va_file: str | PathLike | None = None, __MCard__=Version(major=2, minor=3, patch=0, prerelease=None, build=None), ignore_checksum: bool = False, pdk_path: str = '', pdk_corner: str = '', op_vars: list[str] | None = None, **kwargs)[source]

Bases: McParameterCollection

DMT class that implements attributes and methods that are common between all ModelCards such as HICUM and BSIM.

Parameters:

nodes_listtuple(str): Port list for this model.
default_subckt_namestr: Default name for the subcircuit to be included.
default_module_namestr: Default name of the module of the VA-File for this device.
versionfloat: Version of the model.
va_filestr, optional: Path to a Verilog-AMS file
circuit{None,:class:~DMT.core.circuit.Circuit}: Circuit to simulate this model card.
mod_namestr: Name of the Model, this is used by EvalTradica, so it must fit there, e.g. ‘HICUM’
level_numstr: Level of the Model, this is used by EvalTradica, so it must fit there, e.g. ‘2’

Attributes:

nodes_listtuple(str): Port list for this model.
circuit{None,:class:~DMT.core.circuit.Circuit}: Circuit to simulate this model card.
default_subckt_namestr: Default name for the subcircuit to be included.
default_module_namestr: Default name of the module of the VA-File for this device.
versionfloat: Version of the model.
va_filestr: Path to a Verilog-AMS file deprecated
va_codes{os.Pathlike: str}: Return the attribute directly
ignore_checksum: bool, optional: If True, the checksum of the save modelcard json is ignored, defaults to False.

get_build_in()[source]: Return the parameters embedded in a build-in model (no Va code and correct module name etc)

get_circuit(use_build_in=False, topology=None, **kwargs) → Circuit[source]

Here the modelcard defines it’s default simulation circuit.

Parameters:

use_build_in{False, True}, optional: Creates a circtui the modelcard using the build-in model
topologyoptional: If a model has multiple standard circuits, use the topology to differentiate between them..

get_verilogae_model() → module[source]

Returns the Verilogae Model for this modelcard

Returns:

ModuleType: The Veriloae-module

Raises:

FileNotFoundError: Raised if no VA-Code is set.

info_json(save_va_code=True, compress_va_code=False, **kwargs)[source]

Returns a dict with serializeable content for the json file to create. Add the info about the concrete subclass to create here!

Parameters:

save_va_code{True, False}, optional: If False, the va_codes are not saved…
compress_va_code{False, True}, optional: If True, the codes are saved using zlib compression and a checksum. See: https://code.activestate.com/recipes/355486-compress-data-to-printable-ascii-data/

classmethod load_json(file_path: str | Path, directory_va_file: str | Path | None = None, ignore_checksum: bool = False) → MCard[source]

Load json file

Just for type hints etc..

Parameters:

file_pathUnion[str, Path]: Path to the json.
directory_va_fileUnion[str, Path, None], optional: If a relative path to a va_file is set in the modelcard, pass the absolute path to the start folder here, by default None. This can be used to load old json modelcards from before saving the full code with the parameters.
ignore_checksumbool, optional: When the code is saved compressed, a checksum is saved with it. If you want to ignore the checksum set this to true, by default False

Returns:

MCard: Loaded modelcard

load_model_parameters(path_to_file, force=True)[source]

Loads the model from a file

The loading method is determined according to the file ending (last 3 characters!!) Possible is “mcp” (see save_model), “txt” or “mat” (planned)

Parameters:

path_to_filestr: Filename (with ending!) including a relative or absolute path
forcebool, optional: If True, values are force set. Set false if bounds from VA-File are used…

print_to_file(path_to_file, file_mode='w', subckt_name=None, module_name=None, line_break='\n')[source]

Generates a spectre .lib file which can be included into an netlist.

Existence of lib file is not checked before writing! Name of File: path_to_file + “.lib”

Parameters:

path_to_filestr or os.Pathlike: Absolute or relative path with file name to the file to generate.
file_modestr, optional: Mode to open the file. Can be used to append :).
subckt_namestr: Name of the subcircuit to be included
module_namestr: Name of the module from the corresponding VA-File
line_breakstr, optional: Is added after each parameter, is used as line breaks.

set_va_codes(path_to_main_code: PathLike | str, version: str | float | None = None)[source]

Sets self._va_codes by extracting all included files from the main file down the include tree.

Parameters:

path_to_main_codeUnion[os.PathLike, str]: Relative or Absolute path to the main Verilog-AMS file
versionUnion[str, float], float: If the given code has a different model version as currently set.

Raises:

NotImplementedError: If a file is included via absolute path.

update_from_vae(remove_old_parameters=False)[source]

Updates the modelcard with information such as parameter boundries and default values, nodes, modules and op vars obtained from the Verilog-A source code using VerilogAE.

Parameters:

remove_old_parametersbool, optional: Deletes parameters which are not part of the VA-Code, by default False

property va_codes: VAFileMap | None[source]

Return the attribute directly

Returns:

VAFileMap